This method refers to the field of electronic circuits and devices, and, mote particularly to a class D amplifier and related methods.
A class-D amplifier is a power D/A converter that is based on the duty-cycle D/A converter topology. Output devices of the amplifier are alternately switched at very high rates between two reference voltages creating a stream of output pulses. Each output pulse is low-pass filtered to remove the constant switching frequency, leaving an output voltage that is proportional to the duty-cycle of the pulse width and the difference of the two reference voltages. The exact switching times of the output devices are determined by the analog or digital audio input signal. With the use of fast and efficient devices in the output stage, high fidelity reproduction of input signals can be created with very little power loss in the amplifier thus allowing more effective delivery to the intended load of a speaker transducer.
2.1. Prior Art #1xe2x80x94Digital Amplifier
A typical digital-input class D amplifier is shown in FIG. 1. Input data is converted from standard audio coding schemes (1-1) to a native magnitude representation. It is then sample rate converted (1-2) for further conversion by a pulse code modulation to pulse width modulation scheme (1-3). This in effect converts magnitude attributes to the time domain for purposes of switch modulation. The switching frequency of the output stage (1-4) of the amplifier is typically chosen at a frequency high enough to allow the output low-pass filter (1-5) to remove the switching frequency for low distortion in the output signal. However, with a switching frequency Fs=300 KHz, a system clock frequency of 300 KHz*216=19 GHz would be required in order to get a pulse width resolution of 16-bits. This unreasonable clock rate illustrates the limitations of this topology for audio CDs and other higher resolution digital formats currently on the market.
2.2. Prior Art #2xe2x80x94Digital Amplifier with Noise-Shaping Filter
A second digital-input class D amplifier topology is shown in FIG. 2. This scheme provides limited audio-band resolution and therefore requires a noise-shaping filter (2-1) to approach acceptable audio quality.
The noise-shaping filter reduces the required resolution of the input signal by placing the quantiser in a feedback loop with a digital filter, such that the filter quantisation error is subtracted from subsequent input samples.
However, system complexity and related risks are increased with the addition of a noise-shaping filter. By placing the quantiser in a feedback loop, artifacts such as jitter, quantisation error and stability limit the practical performance. Also, increasing the noise-shaping filter""s order beyond three offers diminishing improvements in performance at reasonable oversampling rates.
2.3. Prior Art #3xe2x80x94Digital Amplifier with Dither Stage
A third prior art shown in FIG. 3 tries to overcome limits in resolution through an analog dithering scheme and is limited by the dithering circuitry. The dithering is accomplished by comparison (3-3) of a voltage generated by a D/A converter (3-1) against an analog ramp generator (3-2). However, quantisation errors of the D/A converter and linearity errors in the ramp generator limit the amount of resolution that may be obtained through the method.
In view of the above background information, it is an object of the present invention to provide an efficient digital amplifier with increased dynamic range, improved linearity and lower total harmonic distortion through unique processing algorithms and the summation of one or mote additional pulse width modulated (PWM output stages.
3.1. Overview
The main blocks of the amplifier include a microprocessor (MCU) or digital signal processor (DSP) (4-1), high-speed control logic (4-2), multiple power output stages (4-3,4-4) and an LC output filter (1-5). The MCU or DSP receives a stream of N-bit audio input data at a sampling rate Fa. Each input sample is split into lower resolution packets that are converted to output pulses by control logic. Each output stage packet contains M pulses that are output at an oversampling rate of Fs=M*Fa. Using a distribution algorithm each output pulse packet is passed to a power output stage. Each output stage is operating at the same switching frequency (Fs), but time-division multiplexed so each output stage is allotted a portion of the switching period. The power supplies (4-11,4-12) of each output stage are ratiometric so that each stage contributes a span of the original input sample. Each output stage span is summed and averaged with a LC low-pass reconstruction filter (4-20) before interfacing to the speaker load (1-6).